This invention relates to semiconductor devices and more particularly to a method for making charge coupled device-complementary metal oxide semiconductor (CCD-CMOS) devices.
In the past, signal processors comprised the combination of a virtual phase-buried channel CCD and either N channel or P channel metal oxide semiconductors (NMOS or PMOS) and their respective fabrication processes. The combination of a CCD and CMOS circuitry was precluded for many reasons, one reason was predicated on the high temperature anneals necessary for CMOS fabrication which are destructive of the CCD and the shorting problems associated with overlapping gates and multi phase CCDs. Those persons skilled in the art desiring detailed information concerning the prior art signal processor are referred to U.S. Pat. No. 4,229,752 issued Oct. 21, 1980 to J. Hynecek for "Virtual Phase Charge Transfer Device." Those persons desiring CMOS background information are referred to U.S. Pat. No. 4,442,591 issued Apr. 17, 1984 to Roger A. Haken for "High Voltage CMOS Process."
The problems attending the use of the prior art processors are, for example, their size per unit area for signal processing, the resulting signal degradation, noise, and marginal charge transfer efficiency (CTE) of the CCD for "imaging" arrays and signal conditioning and power consumption attending the use of NMOS or PMOS.